• DocumentCode
    3191882
  • Title

    An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems

  • Author

    Lee, Jason D. ; Gupta, Nikhil ; Bhojwani, Praveen S. ; Mahapatra, Rabi N.

  • Author_Institution
    Texas A&M Univ., College Station
  • fYear
    2008
  • fDate
    17-19 March 2008
  • Firstpage
    184
  • Lastpage
    189
  • Abstract
    As embedded and safety-critical applications begin to employ many-core SoCs using sophisticated on-chip networks, ensuring system quality and reliability becomes increasingly complex. Infrastructure IP has been proposed to assist system designers in meeting these requirements by providing various services such as testing and error detection, among others. One such service provided by infrastructure IP is concurrent online testing (COLT) of SoCs. COLT allows system components to be tested in-field and during normal operation of the SoC However, COLT must be used judiciously in order to minimize excessive test costs and application intrusion. In this paper, we propose and explore the use of an anomaly-based test triggering unit (ATTU) for on-demand concurrent testing of SoCs. On-demand concurrent testing is a novel solution to satisfy the conflicting design constraints of fault-tolerance and performance. Ultimately, this ensures the necessary level of design quality for safety-critical applications. To validate this approach, we explore the behavior of the ATTU using a NoC-based SoC simulator. The test triggering unit is shown to trigger tests from test infrastructure IP within 1 ms of an error occurring in the system while detecting 81% of errors, on average. Additionally, the ATTU was synthesized to determine area and power overhead.
  • Keywords
    embedded systems; error detection; fault tolerant computing; integrated circuit design; integrated circuit reliability; integrated circuit testing; network-on-chip; NoC-based SoC simulator; NoC-based safety-critical systems; SoC; anomaly-based test triggering unit; concurrent online testing; error detection; fault tolerance design constraints; infrastructure IP cores; test triggering mechanism; Application software; Computer science; Degradation; Electronic equipment testing; Fault tolerance; Hardware; Monitoring; Network-on-a-chip; System testing; Thermal stresses; network on chip; on-line test; test triggering;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-0-7695-3117-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2008.4479723
  • Filename
    4479723