Title :
A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS
Author :
Benkeser, C. ; Bubenhofer, A. ; Huang, Q.
Author_Institution :
Integrated Syst. Lab., ETH Zurich, Zurich, Switzerland
Abstract :
This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multi-mode architecture is implemented in 0.13 μm CMOS technology occupying 1.0 mm2 and dissipating only 1.3 mW in fastest EDGE data transmission mode.
Keywords :
3G mobile communication; CMOS digital integrated circuits; application specific integrated circuits; cellular radio; radio receivers; CMOS technology; EDGE data transmission mode; GSM-GPRS-EDGE; digital baseband receiver ASIC; power 1.3 mW; size 0.13 mum; Baseband; Channel estimation; GSM; Measurement; Modulation; Random access memory; Receivers; 2.5G; 2G; Baseband; EDGE; EGPRS; Equalizer; GSM; Low Power; Mobile Communication; Receiver;
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
DOI :
10.1109/VLSISOC.2010.5642592
