Design and Implementation of a Co-Processor for Providing Data Protection in Embedded Systems

This paper presents the design and implementation of a Co-Processor (CP), which can provide the basic blocks for data protection in embedded systems. This Co-processor can be used for forward error correction, random number generation and hash generation. It performs forward error correction using BCH and Reed Muller algorithms, non-deterministic random number generation and hash generation using SHA-1 algorithm. This can be interfaced with any 16-bit processor using 6-bit address bus, control signals and interrupt pins. The co-processor is verified initially using Altera ACEX FPGAs along with complete system interface targeting to 50 MHz clock frequency. The design is carried out in 1.0 um CMOS standard cell technology and timing paths are verified with static timing analysis tool targeting 20ns clock period.