Title :
Processor Verification with hwBugHunt
Author :
Sudhakrishnan, Sangeetha ; Su, Liying ; Renau, Jose
Author_Institution :
Univ. of California Santa Cruz, Santa Cruz
Abstract :
Functional verification of modern processors and complex ASIC designs is a challenging task. Verification is frequently more complex than the design itself. The time required to find the exact source of an error in complex designs represents a significant part of the verification process. Most test suites only report the existence of a bug, but are unable to ultimately discover the line of HDL code where the bug is located. Designing new tools and techniques that reduce these overheads is very important to keep the verification costs under control. This paper proposes a novel HDL error-discovery tool (hwBugHunt) to pinpoint the line of code where a bug is located. hwBugHunt works by instrumenting Verilog code and gathering statistics during the execution of various test benches. The proposed infrastructure is tested on an Alpha-like 21264 Verilog implementation. Our evaluation shows that hwBugHunt pinpoints 62% of the bugs introduced on IVM, and it does so with a low overhead and high accuracy.
Keywords :
formal verification; hardware description languages; microprocessor chips; Alpha-like 21264 Verilog implementation; HDL error-discovery tool; Verilog code; hwBughunt tool; processor verification; Application specific integrated circuits; Computer bugs; Costs; Design engineering; Fault diagnosis; Hardware design languages; Instruments; Out of order; Process design; Testing;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479730