DocumentCode
3192024
Title
Increasing data TLB resilience to transient errors
Author
Li, Feihui ; Kandemir, Mahmut
Author_Institution
Comput. Sci. & Eng., Pennsylvania State Univ., USA
fYear
2005
fDate
11-12 May 2005
Firstpage
297
Lastpage
298
Abstract
This paper first demonstrates that a large fraction of data TLB entries are dead (i.e., not used again before being replaced) for many applications at any given time during execution. Based on this observation, it then proposes two alternate schemes that replicate actively accessed data TLB entries in these dead entries to increase the resilience of the TLB against transient errors.
Keywords
cache storage; data structures; digital storage; memory architecture; data TLB resilience; data access; dead data TLB entries; transient errors; Application software; Computer errors; Computer science; Data engineering; Error analysis; Error correction; Error-free operation; Hardware; Protection; Resilience;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.43
Filename
1430162
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