RITC: repeater insertion with timing target compensation

This paper investigates the problem of repeater insertion for global interconnects under given timing constraints. A novel technique is proposed to aggressively reduce the positive timing slack for maximal repeater reduction while maintaining timing closure. Our scheme is both fast and effective due to the judicious combination of accurate SPICE simulations and the simple Elmore delay model. In comparison with other repeater insertion solvers, our scheme achieves up to 41% reduction in total repeater width in comparable runtimes.