DocumentCode
3192079
Title
Timing-Aware Multiple-Delay-Fault Diagnosis
Author
Mehta, V.J. ; Marek-Sadowska, M. ; Kun-Han Tsai ; Rajski, J.
Author_Institution
Univ. of California, Santa Barbara
fYear
2008
fDate
17-19 March 2008
Firstpage
246
Lastpage
253
Abstract
With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that these errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay fault diagnosis problem and propose a novel, simulation-based approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower- than-nominal clock frequencies. We experimentally determined our diagnosis algorithm s sensitivity to delay variations.
Keywords
automatic test pattern generation; fault simulation; integrated circuit testing; timing; delay variation; design timing; diagnosis algorithm; timing-aware multiple-delay-fault diagnosis; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Clocks; Delay estimation; Failure analysis; Fault diagnosis; Frequency estimation; Timing; ATPG; DFT; defect-diagnosis; delay-testing; diagnosis;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
978-0-7695-3117-5
Type
conf
DOI
10.1109/ISQED.2008.4479734
Filename
4479734
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