An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

A high performance digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy to identify the pixels to be fed to different processing elements helps reducing the data storage requirements in the circuitry. The new design results in 75% reduction in multipliers and 50% reduction in adders when compared with the conventional systolic architecture. The proposed architecture design is capable of performing convolution operations with 14×14 kernel at a rate of 57 1024×1024 frames per second in a Xilinx ´s Virtex 2v2000ff896-4 FPGA.