• DocumentCode
    3192197
  • Title

    Architecting for Physical Verification Performance and Scaling

  • Author

    Ferguson, John ; Todd, Robert

  • Author_Institution
    Mentor Graphics Corp., Beaverton
  • fYear
    2008
  • fDate
    17-19 March 2008
  • Firstpage
    283
  • Lastpage
    288
  • Abstract
    The primary goal when using physical verification tools is to achieve the best performance at the lowest cost, both in resources and time. Physical verification tools rely on multiple enabling technologies to contribute to runtime and turnaround time reduction. Using differing combinations of architecture and scaling, this paper compares and contrasts three physical verification approaches to determine the combination of factors most likely to produce the desired results in a production environment.
  • Keywords
    integrated circuit design; nanoelectronics; multiple enabling technologies; nanometer IC design; physical verification performance; runtime reduction; scaling; turnaround time reduction; Cooling; Costs; Debugging; Delay effects; Explosions; Graphics; Hardware; Production; Runtime; Testing; physical verification performance; resource optimization; scaling; scaling comparisons; turnaround time reduction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-0-7695-3117-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2008.4479740
  • Filename
    4479740