Low-power hardware for neural spike compression in BMIs

Author

Lapolli, Angelo C. ; Coppa, B. ; Heliot, R.

Author_Institution

CEA-LETI, Grenoble, France

fYear

2013

fDate

3-7 July 2013

Firstpage

2156

Lastpage

2159

Abstract

Within brain-machine interface systems, cortically implanted microelectrode arrays and associated hardware have a low-power budget for data sampling, processing, and transmission. Recent studies have shown the feasibility of data transmission rate reduction using compressed sensing on detected neural spikes. They provide power savings while maintaining clustering and classification abilities. We propose and analyze here a low-power hardware implementation for spike detection and compression. The resulting integrated circuit, designed in CMOS 65nm technology, consumes 2.83 μW and provides 97% of data rate reduction.

Keywords

CMOS integrated circuits; biomedical electrodes; brain-computer interfaces; compressed sensing; low-power electronics; medical signal detection; microelectrodes; neural nets; neurophysiology; pattern clustering; prosthetics; signal classification; signal sampling; BMI; CMOS technology; brain-machine interface system; classification ability; clustering ability; compressed sensing; cortically implanted microelectrode arrays; data processing; data sampling; data transmission rate reduction; integrated circuit; low-power hardware; neural spike compression; neural spike detection; power 2.83 muW; size 65 nm; Band-pass filters; Compressed sensing; Detectors; Encoding; Generators; Hardware; Microelectrodes; Brain-Machine Interface; Compressed Sensing; Integrated circuits; Neural signals processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering in Medicine and Biology Society (EMBC), 2013 35th Annual International Conference of the IEEE

Conference_Location

Osaka

ISSN

1557-170X

Type

conf

DOI

10.1109/EMBC.2013.6609961

Filename

6609961