Title :
Static ultra-low-voltage high-speed CMOS logic and latches
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present timing details for static ultra-low-voltage (ULV) CMOS inverters and latches. The logic presented resemble domino CMOS logic and is more than 10 times as fast as complementary CMOS for very low supply voltages. Static ULV inverters and latches are presented and preliminary simulated data are provided for a 90 nm TSMC CMOS process.
Keywords :
CMOS logic circuits; flip-flops; invertors; TSMC CMOS process; ULV CMOS inverters; latches; resemble domino CMOS logic; size 90 nm; static ultra-low-voltage high-speed CMOS logic; CMOS integrated circuits; Clocks; Delay; Inverters; Latches; Logic gates; Transistors;
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
DOI :
10.1109/VLSISOC.2010.5642610
