DocumentCode
3192290
Title
An improved RNS generator 2n ± k based on threshold logic
Author
Pettenghi, Hector ; Chaves, Ricardo ; Sousa, Leonel ; Avedillo, María J.
Author_Institution
IST/INESC-ID, Lisbon, Portugal
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
119
Lastpage
124
Abstract
This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2n ± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date.
Keywords
residue number systems; threshold logic; RNS generator; residue generators; threshold logic; Arrays; Delay; Generators; Logic gates; System-on-a-chip; Topology; Very large scale integration; binary-to residue number systems converter; generator modulo A; residue number systems; threshold logic;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location
Madrid
Print_ISBN
978-1-4244-6469-2
Type
conf
DOI
10.1109/VLSISOC.2010.5642611
Filename
5642611
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