Synchronous duty cycle correction circuit

A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the input of the circuit is used which narrows the input duty cycle range to the circuit core. We achieved deterministic delay between rising edges of the input and output clock signals, defined as four inverting stages only, that allowed successful integration of the circuit into the custom clock tree structure in a system-on-chip, keeping the same clock delay for all its branches: having corrected and not corrected duty cycle.