DocumentCode
3192425
Title
An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector
Author
Lin, Ding-Guo ; Lu, Bing-Hsun ; Chiueh, Herming
Author_Institution
Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
101
Lastpage
104
Abstract
In this paper, a glitch-free DLL-based clock generator using a feedback-switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detectors to eliminate undesired glitch problem which is generated by switching feedback stage of a DLL. The clock generator can generate clock signals ranging from 100MHz to 1.6GHz. The peak to peak jitter is 23.168ps and power consumption is 37.8mW at 1.6GHz. The proposed clock generator is implemented in TSMC 0.18μm process and occupies only 0.039 mm2 which is suitable for the power management systems.
Keywords
circuit feedback; clocks; delay lock loops; detector circuits; jitter; signal generators; switching circuits; TSMC process; feedback-switching detector; frequency 100 MHz to 1.6 GHz; glitch-free DLL-based clock generator; jitter; power 37.8 mW; programmable power management system; size 0.18 mum; Clocks; Delay; Detectors; Generators; Image edge detection; Phase frequency detector; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location
Madrid
Print_ISBN
978-1-4244-6469-2
Type
conf
DOI
10.1109/VLSISOC.2010.5642615
Filename
5642615
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