Interconnect limits on gigascale integration (GSI)

Summary form only given. Throughout the past four decades, silicon semiconductor technology has been advancing at exponential rates in both productivity and performance. In the physical world, such exponential advances cannot continue endlessly. A systematic assessment of early 21st century opportunities for GSI reveals an increasingly troublesome dichotomy. As minimum feature sizes continue to scale to ever smaller dimensions, transistor switching delay diminishes continuously while interconnect latency increases monotonically. The impact of this dichotomy can be moderated significantly by: (1) new materials and processes to reduce interconnect conductor resistivity and insulator permittivity; (2) reverse or smart scaling that optimizes the architecture of a multilevel wiring network to satisfy a complete set of performance specifications; and (3) new chip microarchitectures and instruction set architectures that serve to keep interconnects short and use longer interconnect paths more judiciously. Smart scaling of global interconnects for a system-on-a-chip (SOC) entails an integrated approach to design of the signal, power, and clock distribution networks. The projected performance of a SOC benefits significantly from novel high density, low cost, compliant lead input/output interconnect technology. Finally, 3D structures including multiple levels of transistors and interconnects provide an opportunity for reducing the length of the longest SOC interconnects and hence increasing global clock frequency