DocumentCode
3192701
Title
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications
Author
Valinataj, Mojtaba ; Mohammadi, Siamak
Author_Institution
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
13
Lastpage
18
Abstract
This paper presents a very low cost routing method to tolerate faulty links and routers in mesh-based Networks-on-Chip (NoC). With reconfigurability, this new algorithm supports irregular topologies caused by faulty components in a network. It concurrently uses both fault and congestion information to route the packets by utilizing only two virtual channels for both fault-tolerance and adaptivity. This method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty components with additional costs. Its performance and overhead are evaluated through appropriate simulations and syntheses. The experimental results show that a significant reliability improvement is achieved against multiple component failures with only a few percent area and power overheads.
Keywords
fault tolerance; network routing; network-on-chip; adaptive routing algorithm; congestion information; mesh-based networks-on-chip; multilevel fault adaptivity; multilevel fault tolerance; power overheads; reconfigurable routing algorithm; Fault tolerance; Fault tolerant systems; Registers; Routing; System recovery; Telecommunication traffic; Network-on-Chip; congestion; fault-tolerance; reconfiguration; reliability; routing algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location
Madrid
Print_ISBN
978-1-4244-6469-2
Type
conf
DOI
10.1109/VLSISOC.2010.5642628
Filename
5642628
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