A Holistic Approach to SoC Verification

Semiconductor designs are continuously growing in complexity. It is no longer practical to view large swaths of waveforms at one time. Dataflow and bus transactions must be presented to engineers in way that will stimulate their creative juices and empower an intuitive understanding of the big picture without unnecessarily cluttering the debug environment. Over time, as technologies enable advanced viewing, navigating and packetizing the waveforms, we migrate to a more artistic approach for understanding complex semiconductor systems. Test environments are bound to grow more complex. Intuitive, visual presentations will support a holistic approach for comprehending and systematically working with increasing complexity instead of getting buried deep into unnecessary details - a need-to-know basis description of the underlying design details. This paper scratches the surface on what such holistic verification solutions will look like by citing examples from existing commercial EDA technologies as well as in- house home-brewed solutions. Examples include design visualization environments that employ hierarchy of signals, color-coding, advanced packet bundling and exploding packet views to foster right-brained thought. Potential future improvements to EDA tools are suggested to show how transaction level models and verification sessions can be presented to give an intuitive feel of the SoC design.