DocumentCode :
3192705
Title :
Plasma charging damage issues in copper single and dual damascene, oxide and low-k dielectric interconnects
Author :
Van den Bosch, Geert ; De Jaeger, Brice ; Tökei, Zsolt ; Groeseneken, Guido
Author_Institution :
IMEC, Leuven, Belgium
fYear :
2001
fDate :
2001
Firstpage :
8
Lastpage :
11
Abstract :
We compared plasma charging damage in single and dual damascene copper wafers with that in classical aluminum back-end-of-line (BEOL) wafers at different antenna levels. In contrast to earlier publications, this comparison is not straightforwardly in favor of the damascene BEOL, but rather depends on the process module (i.e. antenna) under consideration. Contact level antennas suffer from more damage in a (single) damascene BEOL as they are sensitive to a larger number of potentially harmful steps. At first glance, via antennas show a better plasma process-induced damage (P2ID) performance than their classical counterparts. However, the layout of a metal trench grid on top of the contact or via holes has a strong impact on P2ID. Considerable damage is still created at the damascene metal-1 level, but it is of a different origin than in an Al BEOL. With respect to the impact of some damascene-specific process steps and materials, it was found that the introduction of novel low-k materials in the IMD stack does not create appreciable changes in P2ID behavior. On the other hand, Cu-barrier sputter deposition might be an issue
Keywords :
copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; permittivity; plasma materials processing; sputter deposition; sputter etching; surface charging; Al-SiO2; Cu; Cu-SiO2; Cu-barrier sputter deposition; IMD stack; P2ID behavior; aluminum back-end-of-line wafers; antenna; antenna levels; contact level antennas; copper dual damascene interconnects; copper single damascene interconnects; copper/low-k dielectric interconnects; copper/oxide interconnects; damascene BEOL; damascene metal-1 level damage; damascene-specific process steps; dual damascene copper wafers; low-k materials; metal trench grid layout; plasma charging damage; plasma process-induced damage performance; process modul; single damascene copper wafers; via antennas; via holes; Artificial intelligence; CMOS technology; Copper; Dielectric materials; Etching; Integrated circuit interconnections; Plasma applications; Silicon carbide; Sputtering; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Plasma- and Process-Induced Damage, 2001 6th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-9651577-5-X
Type :
conf
DOI :
10.1109/PPID.2001.929966
Filename :
929966
Link To Document :
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