Title :
Plasma induced damage testing methodology for the 0.13 μm CMOS technology
Author :
Cismaru, C. ; Ramanathan, V.
Author_Institution :
Conexant Syst. Inc., Newport Beach, CA, USA
Abstract :
In this work, we investigate various testing methodologies for the evaluation of plasma induced damage to CMOS devices in the 0.13 μm technology. Results show that threshold voltage shift measurements of test structures with various antenna ratios at sub-20 Å gate oxide thickness are no longer a good indicator of plasma induced damage. Instead, gate leakage measurement techniques with and without voltage stress are more sensitive. This allows for the use of very simple two-terminal CMOS devices for plasma-induced damage evaluation. Furthermore, testing conditions for gate leakage current are investigated. The low voltage measurements showed the most sensitivity to plasma induced damage
Keywords :
CMOS integrated circuits; integrated circuit reliability; integrated circuit testing; leakage currents; plasma materials processing; surface charging; surface treatment; 0.13 micron; 20 angstrom; CMOS devices; CMOS technology; SiO2-Si; antenna ratios; gate leakage current; gate leakage measurement techniques; gate oxide thickness; low voltage measurements; plasma induced damage; plasma induced damage testing methodology; plasma-induced damage evaluation; sensitivity; test structures; testing conditions; testing methodologies; threshold voltage shift measurements; two-terminal CMOS devices; voltage stress; Antenna measurements; CMOS technology; Gate leakage; Measurement techniques; Plasma devices; Plasma measurements; Testing; Thickness measurement; Threshold voltage; Voltage measurement;
Conference_Titel :
Plasma- and Process-Induced Damage, 2001 6th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-9651577-5-X
DOI :
10.1109/PPID.2001.929976
