DocumentCode :
3192881
Title :
A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders
Author :
Chandrasetty, Vikram Arkalgud ; Aziz, Syed Mahfuzul
Author_Institution :
School of Electrical and Information Engineering, University of South Australia, Mawson Lakes, 5095, Australia
fYear :
2011
fDate :
11-15 July 2011
Firstpage :
1
Lastpage :
7
Abstract :
A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.
Keywords :
Digital communication; cyclic codes; error correction codes; field programmable gate array; flexible structures; logic design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia and Expo (ICME), 2011 IEEE International Conference on
Conference_Location :
Barcelona, Spain
ISSN :
1945-7871
Print_ISBN :
978-1-61284-348-3
Electronic_ISBN :
1945-7871
Type :
conf
DOI :
10.1109/ICME.2011.6011832
Filename :
6011832
Link To Document :
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