A novel copper interconnection technology using self aligned metal capping method

Author

Saito, Tatsuyuki ; Imai, Toshinori ; Noguchi, Junji ; Kubo, Maki ; Ito, Yuko ; Omori, Sohei ; Ohashi, Naofumi ; Tamaru, Tsuyoshi ; Yamaguchi, Hizuru

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2001

fDate

6-6 June 2001

Firstpage

15

Lastpage

17

Abstract

A self aligned metal capping process for Copper damascene interconnect is newly developed in this study. A tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 μm bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation speed are evaluated.

Keywords

CMOS integrated circuits; chemical vapour deposition; copper; integrated circuit interconnections; integrated circuit reliability; CVD; Cu; Cu damascene interconnect; W; W capping layer; bipolar-CMOS LSI; multilevel Cu interconnects; operation speed; reliability; self aligned metal capping; yield; CMOS technology; Copper; Delay; Dielectrics; Hydrogen; Large scale integration; Optical films; Reflectivity; Silicon compounds; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Conference_Location

Burlingame, CA, USA

Print_ISBN

0-7803-6678-6

Type

conf

DOI

10.1109/IITC.2001.930003

Filename

930003