DocumentCode :
3193351
Title :
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm)
Author :
Talapatra, Somsubhra ; Rahaman, Hafizur
Author_Institution :
Dept. of Inf. Technol., Bengal Eng. & Sci. Univ. (BESU), Howrah, India
fYear :
2010
fDate :
27-29 Sept. 2010
Firstpage :
219
Lastpage :
224
Abstract :
In this paper, a scalable VLSI multiplication architecture based on Montgomery multiplication (MM) algorithm for elliptic curve cryptography (ECC) over GF(pm), where p is a positive prime and m is the degree of extension of the base field GF(p), is presented. The elements of the GF(pm) are in polynomial basis (PB) representation. The coefficients of the polynomials are represented in Montgomery residue format to simplify the multiplications over GF(p). The proposed algorithm of MM over GF(pm) requires m(m+1) MMs and m2 additions over GF(p). However, the proposed architecture takes {m(m+1)Nmm+Nadd +1} cycles to compute MM over GF(pm), where Nmm > Nadd = 2, and Nmm and Nadd are the numbers of cycles to complete an MM and an addition over GF(p), respectively. The security of an ECC scheme depends on the number of elements in GF(pm). Hence, for a p with nominal bit length (p≫2), the value of m can be small, but the GF(pm) still contains almost equal number of elements to a GF(2k), where k is positive integer. The complexity of the MM architecture over GF(p) is reduced by using carry-save-adder (CSA) based implementation, where NPE is the depth of the CSA. Analysis shows that the area complexity of the proposed architecture is significantly less. Implementation in AMS-0.35um technology, with L=30 (for p=536872717), m=23 and NPE=8, yields a clock frequency of 20.885 MHz, throughput of 6243.68 multiplications per second and power consumption of 86.8 mW (at 20 MHz).
Keywords :
VLSI; arithmetic; polynomials; public key cryptography; carry-save-adder; elliptic curve cryptography; low complexity Montgomery multiplication architecture; polynomial basis representation; scalable VLSI multiplication architecture; Adders; Complexity theory; Computer architecture; Delay; Polynomials; Registers; Very large scale integration; Montgomery multiplication; VLSI; binomial; carry-save-adder; elliptic curve cryptography; finite field;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
Type :
conf
DOI :
10.1109/VLSISOC.2010.5642663
Filename :
5642663
Link To Document :
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