DocumentCode
319342
Title
A stochastic method for defect level analysis of pseudorandom testing
Author
Jone, Wen-Ben ; Das, Sunil R.
Author_Institution
Dept. of Comput. Sci., Nat. Chung-Cheng Univ., Chiayi, Taiwan
fYear
1998
fDate
4-7 Jan 1998
Firstpage
382
Lastpage
385
Abstract
Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. Although our discussions are primarily based on the single stuck-at fault model, it is not difficult to extend the results to other fault types
Keywords
Markov processes; VLSI; built-in self test; integrated circuit modelling; integrated circuit testing; statistical analysis; stochastic processes; Markov model; VLSI circuit detectability; built-in self-testing; defect level analysis; differential equation; fabrication yield; pseudorandom testing; single stuck-at fault; statistical analysis; stochastic method; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Differential equations; Performance analysis; Performance evaluation; Sequential analysis; Stochastic processes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location
Chennai
ISSN
1063-9667
Print_ISBN
0-8186-8224-8
Type
conf
DOI
10.1109/ICVD.1998.646638
Filename
646638
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