DocumentCode
3193440
Title
Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process
Author
Tian, Ruiqi ; Boone, Robert ; Chheda, Sejal ; Smith, Brad ; Tang, Xiaoping ; Travis, Ed ; Wong, D.E.
Author_Institution
Motorola Inc., Austin, TX, USA
fYear
2001
fDate
6-6 June 2001
Firstpage
48
Lastpage
50
Abstract
In a trench-first-via-last (TFVL) dual-inlaid metal process, the thickness of resist coated in the via definition step after trench formation varies according to underlying trench topography. Variation in resist thickness reduces via size uniformity and thus process window. Based on the modeling of resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity. Experimental results show significantly enlarged process window after proximity dummy features are inserted.
Keywords
dielectric thin films; integrated circuit metallisation; proximity effect (lithography); resists; semiconductor process modelling; surface topography; TFVL dual-inlaid metal process; layout modifications; nearby trench densities; process uniformity; process window; proximity dummy feature placement; proximity dummy features; resist; resist thickness; selective via sizing; size uniformity; thickness; trench formation; trench topography; trench-first-via-last dual-inlaid metal process; via definition step; weighted sum; Dielectrics; Integer linear programming; Lead; Production; Resists; Semiconductor device modeling; Surface tension; Surface topography;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International
Conference_Location
Burlingame, CA, USA
Print_ISBN
0-7803-6678-6
Type
conf
DOI
10.1109/IITC.2001.930013
Filename
930013
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