Title :
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions
Author :
Zhu, Dan ; Li, Tun ; Guo, Yang ; Li, Si-Kun
Author_Institution :
Nat. Univ. of Defense Technol., Changsha
Abstract :
Symbolic simulation-based approach is viable for the sequential equivalence checking (SEC) of SLM-vs.-RTL. However, it can\´t avoid the storage explosion introduced by the explosion of the BDD sizes for large designs. For scalability, we introduce two kinds of decomposition techniques: One is the equivalence checking oriented program slicing; the other is the hierarchical insertion of logic cut- points. And a 2D decomposition SEC method of SLM-vs.-RTL is presented. "2D decomposition" means decomposition in the space dimension and the time dimension. The verification model is only built for the program slices of a single output variable for each time, which limits the usage of memory. During checking the equivalence of the program slices, the logic cutpoints are inserted to split the verification model of the program slices in the time dimension, which controls the storage explosion further. The promising experimental results demonstrate the benefits brought by our 2D decomposition method.
Keywords :
decomposition; logic design; program slicing; program verification; sequential circuits; 2D decomposition; RTL descriptions; logic cutpoints; oriented program slicing; program verification; register transfer level; scalability; sequential equivalence checking; space dimension; system level; time dimension; Binary decision diagrams; Circuit simulation; Computational modeling; Computer science; Computer simulation; Data structures; Explosions; Hardware design languages; Logic; Scalability; Program slicing; Sequential equivalence checking; cutpoints;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479812