DocumentCode
3193597
Title
DRAM performance improvement by lowering interconnect capacitance
Author
Li, Weimin ; Sandhu, Gurtej S. ; Cho, Chih-Chen ; Blalock, G.D.
Author_Institution
Micron Technol. Inc., Boise, ID, USA
fYear
2001
fDate
6-6 June 2001
Firstpage
78
Lastpage
80
Abstract
SiOC low k (k∼3.0) ILD was successfully integrated into a 0.18 μm Synchronous DRAM (SDRAM) with high yields in probe, backend and QA reliability tests. As a result, the bitline capacitance (Cbit) was reduced by 8%. The refresh, speed and power consumption performances were significantly improved.
Keywords
DRAM chips; VLSI; aluminium; capacitance; dielectric thin films; integrated circuit interconnections; 0.18 micron; Al; C-doped SiO/sub x/ films; DRAM performance improvement; SDRAM; SiO:C; SiOC; SiOC inter-layer dielectric; SiOC low k ILD; bitline capacitance; interconnect capacitance reduction; power consumption performance; refresh performance; speed performance improvement; synchronous DRAM; Capacitors; Conducting materials; Electrical capacitance tomography; Logic; Materials reliability; Probes; Random access memory; SDRAM; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International
Conference_Location
Burlingame, CA, USA
Print_ISBN
0-7803-6678-6
Type
conf
DOI
10.1109/IITC.2001.930023
Filename
930023
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