High performance and low cost entropy encoder for H.264 AVC baseline entropy coding

This paper presents a high performance and low cost architecture for H.264/AVC baseline profile entropy encoder. In the proposed design, an efficient method is used to design CAVLC to reduce the hardware cost. The regularity of nC calculation allows the architecture in reducing area. With the synthesis constraint of 100Mhz clock, the logic gate count of the proposed design is 16K gates based on a 0.18 mum TSMC cell library. The power consumption of the proposed hardware is 2.5mW at 27Mhz and 1.8V. The implemented architecture can achieve the real-time processing requirement for HD 1080 format video sequences.