DocumentCode
3193637
Title
High efficient NTSS-based parallel architecture for motion estimation in H.264
Author
Ho, Mean-Hom ; Huang, Jau-Jiun ; Chin, Shang-Chiang ; Hsu, Chun-Lung
Author_Institution
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien
fYear
2008
fDate
25-27 May 2008
Firstpage
679
Lastpage
683
Abstract
This paper proposes a parallel architecture design for motion estimation (ME) by using the new three step search (NTSS) block-matching algorithm. The proposed NTSS-based parallel architecture adopts the partition technique to separate the encoded frame into two parts for operating. By using the partition technique, the search time of the proposed NTSS-based parallel architecture can be reduced more than 1/2 times. In other words, the proposed NTSS-base parallel architecture design produces efficient solution for real-time ME required in video application with high speed requirement. Experimental results show that the proposed architecture is the best tradeoff in terms of hardware area overhead and speed among the all-existing previous works. Also, the proposed architecture design can be used for various video applications from low bit-rate video to HDTV system.
Keywords
high definition television; motion estimation; parallel architectures; video coding; H.264; HDTV system; NTSS-based parallel architecture; block matching; hardware area overhead; low bit-rate video; motion estimation; new three step search; video applications; Computer architecture; Electronic mail; IEC standards; ISO standards; Motion estimation; Parallel architectures; Transform coding; Video coding; Video compression; Video sequences;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location
Fujian
Print_ISBN
978-1-4244-2063-6
Electronic_ISBN
978-1-4244-2064-3
Type
conf
DOI
10.1109/ICCCAS.2008.4657864
Filename
4657864
Link To Document