A low-power, high-speed DCT architecture for image compression: Principle and implementation

We present a new design of low-power and high-speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs). The proposed compression method converts the image to be compressed in many lines of 8 pixels and then applies our optimized 1D-DCT algorithm for compression. The DCT optimization is based on the hardware simplification of the multipliers used to compute the DCT coefficients. In fact, by using constant multipliers based on Canonical Signed Digit (CSD) encoding, the number of of adders, subtracters and registers will be minimum. To further decrease the number of required arithmetic operators, a new technique based on Common Subexpression Elimination (CSE) is examined. FPGA implementations prove that the CSE implies less computations, less material complexity and a dynamic power saving of about 22% at 110 MHz of clock frequency in Spartan3E device.