A bitonic-sorter based VLSI implementation of the M-algorithm

Author

Simmons, Stanley J.

Author_Institution

Dept. of Electr. Eng., Queen´´s Univ., Kingston, Ont., Canada

fYear

1989

fDate

1-2 June 1989

Firstpage

337

Lastpage

340

Abstract

An implementation of the M-algorithm based on a bitonic sorter is proposed for VLSI implementation. The sorting network is already proven. The sorting architecture is well matched to the use of a few high-speed pipelined path extender units. Such units are highly specific to the trellis being decoded, but it is generally possible to fit several on one chip. The architecture is readily extended to larger M with only a small fractional decrease in decoding rate.<>

Keywords

VLSI; decoding; encoding; M-algorithm; VLSI implementation; bitonic sorter; breadth-first search algorithm coding; decoding; high-speed pipelined path extender units; sorting architecture; Communication channels; Decoding; Image coding; Parallel processing; Proposals; Sorting; Source coding; Speech; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC, Canada

Type

conf

DOI

10.1109/PACRIM.1989.48371

Filename

48371

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3193673