Implementation Considerations for a Sub-sampling Impulse Radio

This paper describes the implementation issues of the proposed sub-sampling impulse radio architecture. By using link budget analysis and system-level simulations with measured pulse and ambient noise, the system specifications of the critical blocks are provided. From circuit implementation perspective, the most challenging block is the high-speed analog-to-digital converter (ADC) which is required to sub-sample RF signals. A low-power, low-cost and fully-integrated CMOS prototype of a sub-sampling ADC has been developed to prove the feasibility of the proposed radio architecture. Finally, a system prototype built with discrete components is used to demonstrate a wireless link