0.18 μm CMOS Power Amplifier for Ultra-Wideband (UWB) System

This paper presents the design and implementation of a single-stage and double-stage power amplifier (PA) for UWB communication system. The proposed PAs are implemented in 0.18 mum CMOS integrated circuit technology for a 3.1-4.8 GHz UWB system. The single-stage PA achieves a simulated maximum power gain of +10.4 dB at an input P1 dB of -5.5 dBm while consuming 23.0 mW of DC dissipation at a DC supply of 1.0 V. Two double-stage PAs have been designed based on the single-stage PA topology. Simulation results for both the double-stage PAs show a maximum power gain of +15.5dB and +24.1 dB respectively with the power consumption of 35.5 mW; and 26.7 mW separately. Results obtained from this study can be used as a reference design for future multi-stage UWB PAs implementation.