Architectural synthesis of DSP circuits under simultaneous error and time constraints

In this paper, the design tasks of wordlength optimization and architectural synthesis are combined. The benefits in comparison to the traditional sequential application of these two tasks are shown. A fine-grain combined wordlength optimization and architectural synthesis based on the use of simulated annealing is presented. As a result, a wider exploration of the design space is possible, thus reducing the implementation costs. The optimizer is tuned for DSP algorithms and is able to simultaneously optimize in terms of implementation area and output noise, thus leading to significant improvements. Moreover, heterogeneous-architecture FPGAs are addressed and the optimization is performed considering both look-up tables (LUTs) and embedded DSP resources. A complete comparison between the traditional sequential approach and the proposed combined approach is provided for FPGAs with and without DSP blocks. Area improvements of up to 21% are reported.