Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits

Author

Jiao, Hailong ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2010

fDate

27-29 Sept. 2010

Firstpage

347

Lastpage

351

Abstract

Ground bouncing noise produced during reactivation events is an important challenge in multi-threshold CMOS (MTCMOS) circuits. A threshold voltage tuning technique based on forward body bias is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits. With the new threshold voltage tuning technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80nm CMOS technology. The design tradeoffs among various important design metrics are evaluated with different data preserving sequential MTCMOS circuits in this paper.

Keywords

CMOS logic circuits; circuit tuning; integrated circuit design; integrated circuit noise; logic design; sequential circuits; UMC CMOS technology; design metrics; forward body bias; ground bouncing noise; multithreshold CMOS circuits; reactivation noise suppression; sequential MTCMOS circuits; threshold voltage tuning technique; Flip-flops; Measurement; Noise; Power demand; Shift registers; Threshold voltage; Transistors; Power gating; data retention; forward body bias; leakage power consumption; noise-aware design; shift register;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP

Conference_Location

Madrid

Print_ISBN

978-1-4244-6469-2

Type

conf

DOI

10.1109/VLSISOC.2010.5642685

Filename

5642685