Temperature- and bus traffic- aware data placement in 3D-stacked cache

As technology scales, increasing capacity of cache memory leads to increase in leakage power dissipation, especially in three-dimensional (3D) IC with high thermal density. In this paper, we explore how cache data can be mapped on a multi-processor architecture in 3D IC to minimize energy consumption with considering temperature distribution and bus traffic congestion. Simulation results based on ILP (Integer Linear Programming) formulation show that the proposed cache data mapping approach achieves up to 30.7% energy reduction compared to the case of considering temperature distribution only.