• DocumentCode
    3193858
  • Title

    Runtime Validation of Transactional Memory Systems

  • Author

    Chen, Kaiyu ; Malik, Sharad ; Patra, Priyadarsan

  • Author_Institution
    Princeton Univ., Princeton
  • fYear
    2008
  • fDate
    17-19 March 2008
  • Firstpage
    750
  • Lastpage
    756
  • Abstract
    Transactional Memory (TM) has been proposed as a promising solution to effectively harness the increasing processing power of emerging multi/many- core systems. While there has been considerable research on the design and implementation of TM systems, it remains to be shown how to address the validation challenge of such systems in face of increasing design bugs and dynamic errors. This paper proposes a runtime validation methodology for ensuring the end-to-end correctness of a TM system. We use an extended constraint graph model to capture the correctness of a transactional execution, and provide efficient hardware support to perform online checking of this constraint graph. We describe the design ideas as well as the key optimization techniques to make this approach practical. Experiments based on a state-of-the-art TM system framework show that our design effectively performs system-level runtime validation with relatively small overhead.
  • Keywords
    integrated circuit design; integrated memory circuits; memory architecture; transaction processing; multicore systems; processing power; runtime validation; transactional memory systems; Computer bugs; Constraint optimization; Design optimization; Error correction codes; Hardware; Logic; Process design; Programming profession; Protection; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-0-7695-3117-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2008.4479832
  • Filename
    4479832