Title :
CMOS multiplexer and demultiplexer for gigabit Ethernet
Author :
Guo, Yawei ; Zhang, Zhanpeng ; Hu, Wei ; Yang, Lianring
Author_Institution :
ASIC & Syst. State Key Lab, Fudan Univ., Shanghai, China
fDate :
29 June-1 July 2002
Abstract :
A multiplexer and a demultiplexer which are suitable for gigabit and 10 gigabit Ethernet are developed using 0.18 μm CMOS technology. Most of the multiplexers and demultiplexers studied in recent years are used in SONET (SDH) systems. Several works are suitable for Ethernet, but their power and area are not optimal. The paper gives a structure to overcome the device limitations of conventional type structures. The new structure is simulated with the 0.18 μm logic CMOS process SPICE model and achieves very high speed. Experimental results are also given.
Keywords :
CMOS digital integrated circuits; SPICE; demultiplexing; demultiplexing equipment; integrated circuit design; local area networks; multiplexing; multiplexing equipment; 0.18 micron; 1 Gbit/s; 10 Gbit/s; CMOS demultiplexer; CMOS multiplexer; SDH; SONET; SPICE; gigabit Ethernet; CMOS logic circuits; CMOS process; CMOS technology; Ethernet networks; Logic devices; Multiplexing; SONET; SPICE; Semiconductor device modeling; Synchronous digital hierarchy;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1180738
