Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation

Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. NBTI is highly sensitive to operating temperature, making the amount of degradation strongly dependent on the thermal history of the chip. In order to accurately predict the amount of threshold voltage increase, the precise temperature profile must be utilized. The existing models are based on the simplified analysis which assumes that the temperature takes up to two possible fixed values over time. These models are inaccurate when predicting the impact of continuously-changing temperature that spans a large range. Our experiments show that proposed model accounting for temperature variation provides a significantly tighter bound for the simulation than that from the model that ignores the temperature variation and assumes a constant (worst-case) temperature. In our experiment, the amount of degradation predicted by the proposed dynamic temperature model is on average 46% less conservative compared to the model based on the worst-case temperature.