Title :
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4
Author :
Krishna, M. Vamshi ; Xie, J. ; Do, M.A. ; Boon, C.C. ; Yeo, K.S. ; Do, Aaron V.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency synthesizer designed using 0.18 μm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 μW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122.4 dBc/Hz at 1MHz offset.
Keywords :
CMOS integrated circuits; IEEE standards; UHF integrated circuits; UHF oscillators; dividing circuits; frequency synthesizers; personal area networks; phase locked loops; phase noise; prescalers; voltage-controlled oscillators; IEEE 802.15.4; P counters; PLL; S counters; duty cycle; frequency 1 MHz; frequency 2.4 GHz; full integrated CMOS frequency synthesizer; integer-N fully programmable divider; phase noise; power 2.8 mW; power 3.6 mW; series quadrature voltage controlled oscillator; size 0.18 mum; true-single-phase-clock prescaler; voltage 1.8 V; word length 6 bit; CMOS integrated circuits; CMOS technology; Frequency synthesizers; Phase noise; Radiation detectors; Transistors; Voltage-controlled oscillators; D flip-flop (DFF); Dual modulus prescalers; Series-QVCO; TSPC; frequency synthesizer; phase-locked loop (PLL);
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
DOI :
10.1109/VLSISOC.2010.5642692
