DocumentCode
3193959
Title
A Basis for Formal Robustness Checking
Author
Fey, Görschwin ; Drechsler, Rolf
Author_Institution
Univ. of Tokyo, Tokyo
fYear
2008
fDate
17-19 March 2008
Firstpage
784
Lastpage
789
Abstract
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are not available yet. In this paper a formal measure for the robustness of a circuit is introduced. Then, a first algorithm to determine the robustness is presented. This is done by reducing the problem either to sequential equivalence checking or to a sequence of property checking instances. The technique also identifies those parts of the circuit that are not robust from a functional point of view and therefore have to be hardened during layout.
Keywords
computability; equivalence classes; integrated circuit reliability; formal robustness checking; property checking instances; sequential equivalence checking; Circuit faults; Circuit simulation; Computer science; Computer science education; Fault tolerance; Formal verification; Robustness; Single event upset; State-space methods; Very large scale integration; Fault models; Formal Methods; Robustness; SAT;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
978-0-7695-3117-5
Type
conf
DOI
10.1109/ISQED.2008.4479838
Filename
4479838
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