Title :
A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth
Author :
Hong, Kuo-Che ; Chiueh, Herming
Author_Institution :
Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A wide-bandwidth low-power CT ΣΔ modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 μm CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time deviator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.
Keywords :
active filters; low-power electronics; pulse shaping; sigma-delta modulation; 4-bit internal quantizer; bandwidth 10 MHz; clock jitter sensitivity; continuous-time sigma-delta modulator; energy 235 fJ; excess loop delay compensation; frequency 320 MHz; low-power medical imaging; modern wireless communications; nonreturn-to-zero DAC pulse shaping; power 36 mW; size 0.18 mum; third-order active-RC loop Alter; voltage 1.8 V; widebandwidth low-power modulator; Bandwidth; Dynamic range; Modulation; Power demand; Signal to noise ratio; Simulation; Solid state circuits;
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
DOI :
10.1109/VLSISOC.2010.5642693