DocumentCode :
3193972
Title :
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations
Author :
Yang, Chengmo ; Orailoglu, Alex
Author_Institution :
Electr. & Comput. Eng., Univ. of Delaware, Newark, DE, USA
fYear :
2010
fDate :
27-29 Sept. 2010
Firstpage :
396
Lastpage :
401
Abstract :
As a result of ever growing integration density and application complexity, future multicore architectures will suffer from increased levels of core availability variations. Full resource utilization in the face of various levels of resource availability necessitates techniques that compactly engender numerous schedules in readiness at compile time. Such schedules, each of which can make maximum utilization of the available resources, can be adaptively applied at runtime, thus enabling a toleration of up to an arbitrarily large amount of resource variations. Core binding permutations furthermore minimize the performance impact imposed by adaptivity on the pre-reconfiguration schedules while retaining all the concomitant benefits. The efficacy of the proposed technique is confirmed by incorporating it into a conventional, widely adopted scheduling heuristic and experimentally verifying it in the context of multiple core deallocations. This paper thus offers critical improvement over prior state-of-the-art, which targets solely single core failures, a subset of resource variation modes in future nanoscale MPSoCs which are projected to display elevated device failures, heat buildup, resource competition and preemptions.
Keywords :
computational complexity; computer architecture; multiprocessing systems; system-on-chip; application complexity; core availability variations; device failures; fully adaptive multicore architectures; multicore architectures; nanoscale MPSoC; prereconfiguration schedules; statically directed dynamic execution reconfigurations; Circuit faults; Conferences; Dynamic scheduling; Resource management; Schedules; System-on-a-chip; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
Type :
conf
DOI :
10.1109/VLSISOC.2010.5642694
Filename :
5642694
Link To Document :
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