InterChip via technology for vertical system integration

Vertical System Integration VSI(R) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device substrates. The I_nterC_hip V_ia (ICV) technology is introduced and discussed as a fully CMOS-compatible wafer-scale process which provides vertical electrical interchip interconnects placed at arbitrary locations, without intervention to the IC´s fabrication technologies. Thinning of the device substrate (150 mm) down to 10 μm as well as bonding it to an other silicon wafer had basically no influence on the electrical performance of EEPROM-products and process monitor structures. Resistances of 2 Ω for a 2×2 μm ² interchip via contact and working contact chains with 480 interchip via contacts are promising results for the future fabrication of multi-layered three-dimensional systems combining the advantages of different device technologies.