Defect and electromigration characterization of a two level copper interconnect

Author

Parikh, S. ; Educato, J. ; Wang, A. ; Zheng, B. ; Wijekoon, K. ; Chen, J. ; Rana, V. ; Cheung, R. ; Dixit, G.

Author_Institution

ECP Div., Appl. Mater. Inc., Santa Clara, CA, USA

fYear

2001

fDate

6-6 June 2001

Firstpage

183

Lastpage

185

Abstract

The effect of annealing conditions on defects and post CMP grain size in electroplated Cu lines is discussed. We have studied the effect of these parameters on interconnect reliability by measuring the electromigration of ´via-fed´ structures. A failure criterion of 2% change in initial resistance was used for EM rather than the traditional 20% used for aluminum interconnect. The electromigration behavior of furnace annealed films is compared to rapid thermal annealed films and the activation energy is found to be in the range of 0.9 to 1.0 eV.

Keywords

annealing; chemical mechanical polishing; copper; electromigration; electroplated coatings; failure analysis; grain size; integrated circuit interconnections; rapid thermal annealing; Cu; activation energy; chemical-mechanical polishing; electromigration; electroplated line; failure analysis; film defect; furnace annealing; grain size; rapid thermal annealing; reliability; two-level copper interconnect; via-fed structure; Annealing; Artificial intelligence; Copper; Corrosion; Dielectrics; Electromigration; Etching; Furnaces; Passivation; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Conference_Location

Burlingame, CA, USA

Print_ISBN

0-7803-6678-6

Type

conf

DOI

10.1109/IITC.2001.930054

Filename

930054