Characteristic impedance determination technique for CMOS on-wafer transmission line with large substrate loss

A characteristic impedance determination technique that can be used in the CMOS process with a large substrate loss is proposed. Furthermore, it is shown using image parameters that the propagation constant is obtained directly from Thru and Line without determining error networks. The validity of the characteristic impedance obtained by the proposed method is shown using the measurement and EM simulation results. The calibration patterns used for the validation check were fabricated using the 40 nm CMOS process.