Characteristic impedance determination technique for CMOS on-wafer transmission line with large substrate loss

Author

Takano, Kyoya ; Amakawa, Shuhei ; Katayama, Kosuke ; Motoyoshi, Mizuki ; Fujishima, Minoru

Author_Institution

Grad. Sch. of Adv. Sci. of Matter, Hiroshima Univ., Higashi-Hiroshima, Japan

fYear

2012

fDate

22-22 June 2012

Firstpage

1

Lastpage

4

Abstract

A characteristic impedance determination technique that can be used in the CMOS process with a large substrate loss is proposed. Furthermore, it is shown using image parameters that the propagation constant is obtained directly from Thru and Line without determining error networks. The validity of the characteristic impedance obtained by the proposed method is shown using the measurement and EM simulation results. The calibration patterns used for the validation check were fabricated using the 40 nm CMOS process.

Keywords

CMOS integrated circuits; electric impedance; nanoelectronics; transmission line theory; CMOS on-wafer transmission line; CMOS process; EM simulation; calibration pattern; characteristic impedance determination technique; image parameter; size 40 nm; substrate loss; thru-reflect-line; Calibration; Impedance; Integrated circuit modeling; Power transmission lines; Propagation constant; Substrates; Transmission line measurements; CMOS; characteristic impedance; distributed constant circuit model; on-wafer measurement; transmission line;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Measurement Conference (ARFTG), 2012 79th ARFTG

Conference_Location

Montreal, QC

Print_ISBN

978-1-4673-1229-5

Electronic_ISBN

978-1-4673-1230-1

Type

conf

DOI

10.1109/ARFTG79.2012.6291203

Filename

6291203