DocumentCode :
3194283
Title :
Instruction set extension for long integer modulo arithmetic on RISC-based smart cards
Author :
Grossschadl, J.
Author_Institution :
Inst. for Appl. Inf. Process. & Commun., Graz Univ. of Technol., Austria
fYear :
2002
fDate :
2002
Firstpage :
13
Lastpage :
19
Abstract :
Modulo multiplication of long integers (≥ 1024 bits) is the major operation of many public-key cryptosystems like RSA or Diffie-Hellman. The efficient implementation of modulo arithmetic is a challenging task, in particular on smart cards due to their constrained resources and relatively slow clock frequency. We present the concept of an application-specific instruction set extension (ISE) for long integer arithmetic. We introduce an optimized multiply-and-accumulate (MAC) unit that makes it possible to compute a×b+c+d with only one instruction, whereby a, b, c, d are single-precision words (unsigned integers). This additional instruction is simple to incorporate into common RISC architectures like the MIPS32. Experimental results show that the inner-product operation of a multiple-precision multiplication can be accelerated by a factor of two without increasing the processor´s clock frequency. We also estimate the execution time of a 1024-bit modulo exponentiation assuming that this special MAC instruction was made available. The proposed ISE is an alternative solution to a crypto co-processor especially for multi-application smart cards (e.g., Java cards) with an embedded 32-bit RISC core.
Keywords :
application specific integrated circuits; digital arithmetic; instruction sets; microprocessor chips; performance evaluation; public key cryptography; reduced instruction set computing; smart cards; MIPS32; RISC; application-specific instruction set extension; clock frequency; crypto coprocessor; execution time; experimental result; exponentiation; long integer modulo arithmetic; modulo multiplication; multiply-and-accumulate unit; public-key cryptosystems; smart cards; Acceleration; Arithmetic; Clocks; Computer aided instruction; Computer architecture; Coprocessors; Frequency; Public key cryptography; Reduced instruction set computing; Smart cards;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture and High Performance Computing, 2002. Proceedings. 14th Symposium on
Print_ISBN :
0-7695-1772-2
Type :
conf
DOI :
10.1109/CAHPC.2002.1180754
Filename :
1180754
Link To Document :
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