Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues

Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200-mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D interconnect process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach, and provides a high-density pin-out alternative to stacked chip-scale packages today.