Title :
Simulating L3 caches in real time using hardware accelerated cache simulation (HACS): a case study with SPECint 2000
Author :
Watson, Myles ; Flanagan, J. Kelly
Author_Institution :
Performance Evaluation Lab., Brigham Young Univ., Provo, UT, USA
Abstract :
Trace-driven simulation is a commonly used tool to evaluate memory-hierarchy designs. Unfortunately, trace collection is very expensive, and storage requirements for traces are very large. In this paper, we introduce HACS (Hardware Accelerated Cache Simulator), and describe the validation methods we used to demonstrate functionality. We also present some initial cache simulation results from SPECint 2000. We then propose future directions for research with HACS.
Keywords :
cache storage; discrete event simulation; field programmable gate arrays; memory architecture; L3 caches simulation; SPECint 2000; hardware accelerated cache simulation; memory-hierarchy designs; storage requirements; trace-driven simulation; Acceleration; Buffer storage; Computational modeling; Computer aided software engineering; Computer science; Computer simulation; Field programmable gate arrays; Hardware; Laboratories; Probes;
Conference_Titel :
Computer Architecture and High Performance Computing, 2002. Proceedings. 14th Symposium on
Print_ISBN :
0-7695-1772-2
DOI :
10.1109/CAHPC.2002.1180766
