Compact resampling algorithm and hardware architecture for paticle filters

In this paper, we propose a compact threshold-based resampling algorithm and architecture for efficient hardware implementation of particle filters. By using a simple threshold-based scheme and assigning each particle a weight independent of its previous value, this resampling algorithm can reduce the complexity of hardware implementation. Simulation results from Matlab indicate that this algorithm has approximately equal performance with the traditional systematic resampling (SR) algorithm when the RMSE is considered. Compact hardware architecture for resampling is presented and the bearings-only tracking problem is used for illustration and evaluation. Experimental study on a Xilinx Virtex 2 pro FPGA platform shows that this hardware architecture is efficient in terms of resource usage and latency.