Title :
ISDN U transceiver algorithm, development system, and performance
Author :
Girardeau, Jim ; Van Bavel, Nick ; Kuenast, Walter ; McCaslin, Shawn ; Pendleton, Matt ; Williams, Tim ; Aly, Sami ; Sayar, Babak ; Hung, Paul ; Koleyni, Ghassem ; Deczky, Andrew ; Ferland, Pierre ; Goulet, Stephane
Author_Institution :
Motorola Semicond., Austin, TX, USA
Abstract :
Motorola and BNR are currently developing the MC145472, a single-chip implementation of a 2B1Q ANSI standard U-interface transceiver for ISDN (integrated services digital network) basic rate access (BRA). The transceiver provides full duplex transmission of 160 kb/s over two-wire nonloaded outside plant loops and is designed to meet the ANSI T1.601 1988 standards for use in both LT and NT1 applications. Its implementation involves state-of-the-art analog and digital signal processing (DSP) technology. The authors describe the functions and verifications of the transceiver, with emphasis on the DSP technology used for echo cancellation, equalization, and timing recovery; the design methodology and hardware testbed used to develop the transceiver algorithms; and performance results for the transceiver under both laboratory and field conditions
Keywords :
ISDN; standards; subscriber loops; transceivers; 160 kbit/s; 2B1Q U interface transceiver; AD 1988; ANSI T1.601 standard; BNR; DSP; ISDN; MC145472 chip; Motorola; U transceiver algorithm; algorithm development system; analog signal processing; basic rate access; digital signal processing; echo cancellation; equalization; hardware testbed; integrated services digital network; timing recovery; two-wire nonloaded outside plant loops; ANSI standards; Design methodology; Digital signal processing; Echo cancellers; Hardware; ISDN; Signal processing algorithms; Testing; Timing; Transceivers;
Conference_Titel :
Global Telecommunications Conference and Exhibition 'Communications Technology for the 1990s and Beyond' (GLOBECOM), 1989. IEEE
Conference_Location :
Dallas, TX
DOI :
10.1109/GLOCOM.1989.64278
